The demand to build smaller/faster/more efficient devices has driven the semiconductor industry over the last decades. As progress in 2D scaling slows other approaches are needed to boost device performance.
Innovations in new materials, architectures (e.g. transistor designs) or innovations by introducing the 3rd dimension are required to further increase logic density.
Evatec sputter equipment like CLUSTERLINE® 300 for processing of 300mm wafers is available in a dedicated CMOS configuration for improved vacuum, defects and contamination performance.
Here are just some of the areas where we can support you so reach out to us in case of any queries.
Interconnect metallization within integrated circuits enables signal transfer between devices. While earlier generations commonly used aluminum, the industry later adopted copper with Ta/TaN barrier layers to meet tighter design rules and reduce resistivity. Today, Evatec supports both traditional and advanced metallization needs with a dedicated CMOS-compatible CLUSTERLINE® 300 system.
Our flexible hardware configurations, including advanced temperature control through cold and hot electrostatic chucks (ESCs), ensure high process repeatability. We offer titanium-aluminum process solutions for higher-level metallization and metal pad formation in applications such as high bandwidth memory (HBM). In addition, our process team is ready to support your development of Ta/TaN barrier and Cu seed processes to meet the demands of next-generation interconnects.
As semiconductor devices become more complex, vertically stacked wafers are increasingly used to achieve higher functional and storage density. One way to overcome the resulting wafer deformation and substrate warpage is backside wafer warpage correction (WPC) through a dielectric PVD layer. Using a compressive nitride PVD solution enables tunable stress films at low temperatures, preserving wafer integrity.
Key specifications for successful WPC include stress range, layer thickness, substrate temperature, edge roll-off, and chemical properties, especially for post-treatment steps such as etch removal.
Hard masks play a crucial role in the manufacturing process of devices, including memories. These masks serve multiple purposes:
However, achieving an effective hard mask involves considering additional factors:
For further information or inquiries, please feel free to contact us.
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Cluster platform architecture with single wafer processing and completely automated handling for front and back metals on 300mm wafers in volume production.
Chip makers face challenges in 3D IC and heterogeneous integration, needing to manage thermal budgets and wafer flatness. Evatec offers solutions for advanced CMOS fabs.