Overview

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Bumping (UBM) 

Bumping, a crucial technique for establishing connections between chips, substrates, and PCBs, involves the creation of raised metal regions known as "bumps" over bonding pads. Evatec offers a comprehensive range of bumping solutions tailored to various applications and specifications. Our advanced bumping processes are available in multiple levels, catering to different pitch requirements, from coarse broad (500um and above) to ultra-fine (less than 50um). By reducing bump size and pitch while ensuring high yield rates, Evatec enhances data transfer speeds and minimizes power consumption, meeting the demands of modern electronic devices. 

One of the primary performance indicators for such interconnects is the contact resistance (Rc). Evatec's state-of-the-art process systems and innovative concepts deliver the industry's lowest contact resistance, ensuring optimal performance and reliability for bonding interconnects. With our cutting-edge technologies and expertise, we enable seamless connectivity and robust functionality in advanced semiconductor packaging applications. 

Fan-Out Wafer Level Packaging (FO-WLP)

Fan-Out Wafer Level Packaging (FO-WLP) emerged to address the challenge of limited space for bumps on chip areas in traditional Wafer Level Chip Scale Packaging (WLCSP). With FO-WLP, the device wafer undergoes dicing, followed by repositioning of individual dies on a carrier wafer, allowing ample space around each die. This reconstituted wafer is then over-molded, creating more room for the redistribution layer (RDL).

Handling substrates with polymers in vacuum tools demands special attention due to their tendency to outgas, potentially contaminating existing layers. At Evatec, our innovative handling solutions ensure efficient processing while mitigating outgassing and minimizing layer contamination, guaranteeing the integrity and quality of the packaging process.

Backside Metallization for Heat Dissipation

High Performance Computing (HPC) is instrumental in various applications, including artificial intelligence, life sciences, and finance. To achieve optimal computing power, advanced system-on-chips (SOCs) or next-generation packaging technologies integrate processors, memory, and storage on die or package levels. However, effective thermal management poses a significant challenge in maximizing computing performance and power efficiency. 

Evatec addresses this challenge through innovative thin film deposition techniques, particularly in backside metallization (BSM). Our BSM solutions facilitate uniform and reliable connections to cooling lids, essential for managing the heat generated by HPC packages. By depositing a solderable layer stack on the wafer's backside, Evatec ensures excellent adhesion, solderability, and minimal film stress. These properties are crucial for meeting stringent thermal requirements and ensuring optimal performance and longevity of HPC systems.